1. Field of the Invention
The present inventi on relates to memory devices and systems including memory management.
2. Description of Related Art
Nonvolatile memory has write/erase endurance limitations. Without memory management with regard to use counts, the memory may wear out prematurely or even cause system failure. Wear leveling for memory management is an approach to increase endurance of nonvolatile memory. Implementation of an effective wear leveling algorithm may consume memory space, increase operating complexity, and cause system overhead and latency. Therefore, it is important to balance the trade-offs between low latency and effective wear leveling. Write/erase endurance limitations for nonvolatile memory such as phase change material based memory can be about 106-109, lower than those of dynamic random access memories (DRAM) which can be more than 1015. Consequently, it can be more important to have effective wear leveling algorithms for nonvolatile memory to be used in high endurance environments like those normally limited to DRAM.
It is desirable to provide an effective wear leveling design that has low computational complexity and low latency, and that can be compatible with existing virtual addressing schemes used for memory management.